1. Field of the Invention
The present invention relates to an LSI (Large Scale Integrated Circuit), a test pattern generating method for a scan path test, an LSI inspecting method and a multichip module. Particularly the invention relates to a method for inspecting an LSI having a power control function or a power-off function, and a method for automatically generating a test pattern by a structured testing technique.
2. Description of the Related Art
In recent years, it has been popular to use structured tests for inspection of LSIs. Examples of the structured tests include a scan path test in which a pattern is generated easily, a BIST (Built In Self Test) in which a pattern is generated inside an LSI, etc. For example, these techniques are described in Miron Abrabmovici and two others, “DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN”, IEEE Press.
The structured testing techniques of LSIs according to the background art are circumstanced as follows. That is, in the techniques, it is assumed that power supplied to each LSI is constant in voltage from the start of a test to the end of the test. In recent years, however, LSIs often have a power control function or a power-off function. Thus, it is impossible to perform inspection including the power control function or the power-off function of each LSI.